The present invention relates to analog circuits generally, and more specifically to switched capacitor circuits.
Switched-capacitor circuits form the core of a wide variety of analog and mixed-signal circuits, including pipelined A/D converters and xcex93) A/D converters. Frequently, these circuits are configured so as to act on the difference between a time-varying input signal and a constant reference signal. For example, FIG. 1A shows a conventional switched-capacitor integrator.
The switched-capacitor integrator shown in FIG. 1A integrates the difference between VIN and a constant reference voltage, VREF. During a first interval (clock phase xcfx861), capacitor 102 (having capacitance C1) acquires a charge equal to C1VIN. Then, during non-overlapping second interval (clock phase xcfx862), an additional charge equal to C1*(VREFxe2x88x92VIN) is forced onto capacitor 102 from the source 120 of voltage VREF; and thus, by charge conservation, at the end of xcfx862, the total charge on capacitor 104 (which has capacitance C2) is equal to
C2* VOUT(nxe2x88x921)xe2x88x92C1*(VREFxe2x88x92VIN)=C2* VOUT(n)
where VOUT(n) is the output of operational amplifier 106 at the end of phase xcfx862 and VOUT(nxe2x88x921) is the output of operational amplifier 106 at the end of the previous xcfx862 phase. As a result, the cycle-by-cycle operation of this circuit follows Equation (1).                                           V            OUT                    ⁡                      (            n            )                          =                                            V              OUT                        ⁡                          (                              n                -                1                            )                                +                                                    C                1                                            C                2                                      ⁢                          (                                                                    V                                          I                      ⁢                                              xe2x80x83                                            ⁢                      N                                                        ⁡                                      (                    n                    )                                                  -                                  V                  REF                                            )                                                          (        1        )            
This is the equation of a discrete-time integrator.
In this configuration, the charge drawn from VREF during the second clock phase xcfx862 is given by C1*(VREFxe2x88x92VIN). This charge is strongly dependent on VIN. If the source 120 of voltage VREF cannot fully settle by the end of phase xcfx862, the result is an integrator gain error, or worse, non-linearity if the circuit is part of an A/D converter.
The derivation of Equation (1) relies on a number of assumptions, including conformance of operational amplifier 106 to ideal properties (infinite gain and infinite bandwidth) and zero impedance at the output of the source 120 of voltage VREF. If either of these assumptions is not met, the circuit of FIG. 1 does not perform precisely as indicated by Equation 1.
Reference is now made to FIG. 2A and an equivalent circuit representation in FIG. 2B. Assume that the reference voltage source 220 has an output resistance, R, and that a large capacitor, having capacitance CBYP, is placed at the output of the voltage source 220 to bypass resistance R at high frequencies. Note that the operational amplifier is not shown in FIGS. 2A and 2B; instead, the bottom plate of capacitor 202 (having capacitance C1) is shown permanently connected to ground. For analytical purposes, this is a valid substitution, because the operational amplifier 106 in FIG. 1 forces the bottom plate or terminal of capacitor 102 (capacitance C1) to a virtual ground.
Assume that CBYP greater than  greater than C1, and that the switching frequency of xcfx861 and xcfx862, FCLK, is much greater than the reciprocal of the time constant RCBYP and also much greater than the bandwidth of VIN. Then, the combination of switches S1 206 and S2 208 and capacitor 202 can be treated as a switched-capacitor resistor 230 (shown in FIG. 2B), with effective value RSC=1/(FCLKC1). As indicated in FIGS. 2A and 2B, VREFxe2x80x2, the xe2x80x9ceffective value of VREF,xe2x80x9d which is the actual voltage sampled by capacitor 202 during clock phase "khgr"2, is then equal to                               V          REF          xe2x80x2                ≈                              V            REF                    -                                    (                                                V                  REF                                -                                  V                                      I                    ⁢                                          xe2x80x83                                        ⁢                    N                                                              )                        ⁢                          R                              R                +                                  R                  SC                                                                                        (        2        )            
Applying this to Equation 1 results in             V      OUT        ⁡          (      n      )        =                    V        OUT            ⁡              (                  n          -          1                )              +                            C          1                          C          2                    ⁢              (                                            V                              I                ⁢                                  xe2x80x83                                ⁢                N                                      ⁡                          (              n              )                                -                                    V              REF              xe2x80x2                        ⁡                          (              n              )                                      )                                                      V            OUT                    ⁡                      (            n            )                          ≈                                            V              OUT                        ⁡                          (                              n                -                1                            )                                +                                                    C                1                                            C                2                                      ⁢                          (                              1                -                                  R                                      R                    SC                                                              )                        ⁢                          (                                                                    V                                          I                      ⁢                                              xe2x80x83                                            ⁢                      N                                                        ⁡                                      (                    n                    )                                                  -                                  V                  REF                                            )                                                          (        3        )            
Thus, the nonzero output impedance of the reference voltage source 220 results in an integrator gain error.
Referring now to FIG. 3, the standard way to address the problem described above is to use a separate capacitor 303 to sample VREF. By using a separate capacitor 303 (with capacitance C3=C1) to sample VREF during phase xcfx862, and then discharging capacitor 303 completely during phase xcfx861, a constant amount of charge is drawn from the reference voltage source 320 in each clock cycle.
In circuit 300, if C3=C1, the difference equation for VOUT(n) is identical to Equation (1). Since capacitor 303 is always discharged to ground during xcfx861, a constant quantity of charge is delivered by VREF on every clock cycle. Thus, there is no signal-dependent error due to nonzero output impedance in the reference source.
Unfortunately, circuit 300 has a number of disadvantages. The additional capacitor 303 in the signal path increases the load on the operational amplifier 306. During the integration phase, xcfx862, there is twice as much capacitance between the inverting operational amplifier input and ground as there is in the circuit 100 in FIG. 1, doubling the load that must be driven by the operational amplifier (C1+C3 vs. C1). This extra load capacitance degrades the setting performance of the operational amplifier. It also reduces the feedback factor, C2/(C1+C3+C2), thus decreasing the closed-loop bandwidth of the switched-capacitor circuit and degrading its settling time. Further, it reduces the closed loop gain of the operational amplifier. In addition, it doubles the thermal (kT/C) noise. Because this circuit has two independent sampling capacitors, the input-referred kT/C thermal noise is 3 dB higher than in the circuit of FIG. 1.
An improved switched capacitor circuit is desired that eliminates signal-dependent error due to nonzero output impedance in the reference source without doubling the load on the operational amplifier.
One aspect of the invention is a circuit assembly, comprising an integrator and first and second capacitors. The first capacitor has a first terminal that is coupled to a first node having a first potential during a first time interval. The first terminal is coupled to a second node at a reference voltage during a second time interval that does not overlap the first time interval. The first capacitor has a second terminal that is coupled to a third node having a common potential during the first time interval. The second terminal is coupled to the integrator during the second time interval. The first capacitor receives a first charge component from the second node that is dependent on the first potential during the second time interval.
The second capacitor has a first terminal that is coupled to a fourth node having a second potential during the first time interval. The common potential is substantially midway between the first and second potentials. The second capacitor provides a second charge component that cancels the first charge component during the second interval.